Title | Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems |
Publication Type | Journal Article |
Year of Publication | 2019 |
Authors | Hedayati, MK, Abdipour, A, Shirazi, RS, Ammann, MJ, John, M, Cetintepe, C, Staszewski, RB |
Journal Title | IEEE Access |
Volume | 7 |
Issue | 1 |
Pagination | 43190-43204 |
Journal Date | 12/2019 |
ISSN Number | 2169-3536 |
Abstract | This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to previous works. The antenna is directly matched to a 2-stage LNA in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm² while the total chip area, including the pad frame, is 1.55×0.85 mm². |
URL | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8668762 |
DOI | 10.1109/ACCESS.2019.2905861 |
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